Metal interconnections in very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits typically consist of interconnect structures containing patterned layers of metal wiring. Typical integrated circuit (IC) devices contain from three to fifteen layers of metal wiring. As feature size decreases and device area density increases, the number of interconnect layers is expected to increase.
The materials and layout of these interconnect structures are preferably chosen to minimize signal propagation delays, hence maximizing the overall circuit speed. An indication of signal propagation delay within the interconnect structure is the RC time constant for each metal wiring layer, where R is the resistance of the wiring and C is the effective capacitance between a selected signal line (i.e., conductor) and the surrounding conductors in the multilevel interconnect structure. The RC time constant may be reduced by lowering the resistance of the wiring material. Copper is therefore a preferred material for IC interconnects because of its relatively low resistance. The RC time constant may also be reduced by using dielectric materials with a lower dielectric constant, k.
High speed logic chips require faster interconnects, as the interconnect delay is now limiting the overall circuit speed. With scaling to smaller dimensions, the interconnect delay becomes a more significant factor limiting overall circuit performance. Throughout the semiconductor industry, interconnect structures using copper conductors within a low-k insulator are being introduced to reduce the interconnect delay. One measure of interconnect delay is the effective dielectric constant k(eff) of the interconnect structure. To obtain a lower k(eff) and hence reduced delay, both a low-k dielectric (k<4) and lower k barriers (e.g., k<7 for silicon nitride) must be used.
State-of-the-art dual damascene interconnect structures comprising low-k dielectric material and copper interconnects are described in “A High Performance 0.13 μm Copper BEOL Technology with Low-k Dielectric,” by R. D. Goldblatt et al., Proceedings of the IEEE 2000 International Interconnect Technology Conference, pp. 261-263. A typical interconnect structure using low-k dielectric material and copper interconnects is shown in FIG. 1. The interconnect structure comprises a lower substrate 10 which may contain logic circuit elements such as transistors. A cap layer 11 may be disposed above lower substrate 10. A dielectric layer 12, commonly known as an inter-layer dielectric (ILD), overlies the substrate 10 and optional cap layer 11. In advanced interconnect structures, ILD layer 12 is preferably a low-k polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). At least one conductor 14, 18 is embedded in ILD layer 12. Conductor 14, 18 is typically copper in advanced interconnect structures, but may alternatively be aluminum or other conductive material. A diffusion barrier liner (not shown) may be disposed between ILD layer 12 and conductor 14, 18. Such diffusion barrier liner may be comprised of tantalum, titanium, tungsten or nitrides of these metals. A cap layer 17 of, e.g., silicon nitride may be disposed on ILD layer 12. The top surface of conductor 18 is made coplanar with the top surface of silicon nitride layer 17, usually by a chemical-mechanical polish (CMP) step. A final cap layer 19, also of, e.g., silicon nitride, may be disposed over the entire structure.
Conductor 14, 18 may be formed by conventional dual damascene processes. For example, formation of the interconnect level shown begins with deposition of ILD material 12 onto cap layer 11. If the ILD material is a low-k polymeric thermoset material such as SiLK™, the ILD material is typically spin-applied, given a post apply hot bake to remove solvent, and cured at elevated temperature. Next, silicon nitride layer 17 is deposited on ILD layer 12. Silicon nitride layer 17, ILD layer 12, and cap layer 11 are then patterned, using a conventional photolithography and etching process, to form at least one trench 18 and via 14. The trenches and vias may be lined with a diffusion barrier liner. The trenches and vias are then filled with a metal such as copper to form conductor 14, 18 in a conventional dual damascene process. Excess metal is removed by a chemical-mechanical polish (CMP) process. Finally, silicon nitride cap layer 19 is deposited on copper conductor 18 and silicon nitride layer 17.
In advanced interconnect structures, a preferable low-k dielectric material is a polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). This material has a dielectric constant of about 2.65. However, copper interconnect structures using such low-k materials as the ILD can suffer from reliability problems, including mechanical failure caused by thermal expansion of the low-k dielectric materials. The modulus of SiLK™ dielectric is 2.7 Gpa, while that of silicon dioxide is 78 Gpa. This difference has been shown to significantly contribute to such reliability problems.
Thus, there is a need in the art for an advanced interconnect structure having a low k(eff) that does not suffer from the reliability problems caused by thermal expansion of polymeric low-k dielectric materials.
U.S. Pat. No. 6,362,091 to Andideh et al. describes an interconnect structure having a multi-layer low-k ILD. Andideh et al. were trying to solve the problem of cracking in relatively brittle low-k carbon-doped silicon films, rather than reliability problems caused by thermal expansion of polymeric low-k dielectric materials. To solve this problem, a multi-layer ILD was proposed comprising alternating layers of a low-k dielectric such as carbon-doped silicon with a second insulating material having increased toughness such as silicon dioxide. Although it is disclosed that the low-k dielectric material may comprise a low-k polymer, it is clear from the disclosure that the problems discussed above with respect to the difference between the modulus for a polymeric low-k dielectric such as SiLK™ and the modulus for silicon dioxide were not recognized by Andideh et al. Moreover, the second insulating materials (having increased toughness) proposed here (SiO2, SiN, SiON, SiOF and SiC) all have relatively high dielectric constants rendering the k(eff) of the multi-layer ILD comparatively high. Finally, the manufacture of this structure is made very difficult by using the same multi-layer ILD for the via level and the line level, with no intermediate cap layer or etch stop layer.
Thus, there is still a need in the art for an advanced interconnect structure having a low k(eff) that does not suffer from the reliability problems caused by thermal expansion of polymeric low-k dielectric materials.